Introduction

This device recreates the logic equations (which can be compiled into a JEDEC fusemap) from read-protected PAL and GAL devices.

Project status

Revision 3 (pictured, leftmost) is currently in development. It supports 20-pin PALs. 24-pin PAL support is implemented in hardware but the software needs additional work to enable reading and analysis of those parts. It also has hardware to accomdate analysis of registered PALs, which is being developed. Consider this a work in progress.

Online documentation and tutorials are here.

Files