Atari GX2 hardware notes (C) 2011 Charles MacDonald ---------------------------------------------------------------------------- CLARN board memory map ---------------------------------------------------------------------------- The address space is sparsely populated and there are a lot of mirror locatiosn. MSB LSB 1100 -00- ---- aaaa aaaa aaa- : DPSRAM (2Kx8 mapped to LSB only) 1100 -aa- ---- aaaa aaaa aaa- : TPC1020 FPGA (4Kx8, but accessible as if it was 2Kx16) 1100 -xx- ---x xxx- ---- --x- : 16V8 GAL strobe area: 1100 -10- ---0 000- ---- --0- : 68RD1# (To half of '244 buffer) 1100 -10- ---0 001- ---- ---- : 68WR# (Write 16-bit DSP comms. latch) 1100 -10- ---0 001- ---- ---- : 68RD0# (Read 16-bit DSP comms. latch) 1100 -10- ---0 010- ---- --0- : CGINT# (To '74 latch) 1100 -10- ---0 011- ---- cba- : COMMLATCH# (To '259 addressable latch) 1100 -11- ---0 000- ---- ---- : LETA# (To pin 23 of unpopulated DIP socket) 1100 -11- ---0 001- ---- --0- : NUMFROTA# (To '273 latch) 1100 -11- ---0 010- ---- cba- : NUMFASEL# (To '259 addressable latch) Officially used locations by Moto Frenzy C80001-C80FFF : DPSRAM CA0000-CA0FFF : FPGA RAM CC0000 : 68RD1# ('244 buffer, bits 7,6 tested as byte only) CC0200 : 68WR#/68RD0# CC0202 : 68WR#/68RD0# (Mirror of CC0200? LXA1 doesn't seem to be by the hardware or GAL to differentiate this address from the other one) CC0400 : CGINT# (w/o) Strobe addresses, a read or write to a listed address affects the latch bit as described. The latch is reset to zero on power-up. CC0600 : COMMLATCH, reset bit 0 (ADSPRES) CC0602 : COMMLATCH, reset bit 1 (ADSPBR) CC0604 : COMMLATCH, reset bit 2 (MOTOR1) CC0606 : COMMLATCH, reset bit 3 (MOTOR2) CC0608 : COMMLATCH, reset bit 4 (/LMASTER) CC060A : COMMLATCH, reset bit 5 (SOL1) CC060C : COMMLATCH, reset bit 6 (SOL2) CC060E : COMMLATCH, reset bit 7 (LED) CC0610 : COMMLATCH, set bit 0 CC0612 : COMMLATCH, set bit 1 CC0614 : COMMLATCH, set bit 2 CC0616 : COMMLATCH, set bit 3 CC0618 : COMMLATCH, set bit 4 CC061A : COMMLATCH, set bit 5 CC061C : COMMLATCH, set bit 6 CC061E : COMMLATCH, set bit 7 CE0000 : LETA# (read only) CE0200 : NUMFROTA (write only) Strobe addresses, a read or write to a listed address affects the latch bit as described. The latch is reset to zero on power-up. CE0400 : NUMFASEL, reset bit 0 CE0402 : NUMFASEL, reset bit 1 CE0404 : NUMFASEL, reset bit 2 CE0406 : NUMFASEL, reset bit 3 CE0408 : NUMFASEL, reset bit 4 CE040A : NUMFASEL, reset bit 5 CE040C : NUMFASEL, reset bit 6 CE040E : NUMFASEL, reset bit 7 CE0410 : NUMFASEL, set bit 0 CE0412 : NUMFASEL, set bit 1 CE0414 : NUMFASEL, set bit 2 CE0416 : NUMFASEL, set bit 3 CE0418 : NUMFASEL, set bit 4 CE041A : NUMFASEL, set bit 5 CE041C : NUMFASEL, set bit 0 CE041E : NUMFASEL, set bit 7 I think the DSACK sizing bits are different for the first 512K of the expansion area, which is why everything is mapped to the latter half (C80000-CFFFFF instead of C00000-C7FFFF) instead. In this region all memory locations are seen as 16-bit only. ---------------------------------------------------------------------------- TPC1020 PLCC pinout ---------------------------------------------------------------------------- 1 - BD12 - 2 - BD13 - 3 - BD15 - 4 - 5V0 Vcc 5 - LXDS# - 6 - BD15 - 7 - RAM.11 - 8 - AAM.17 - 9 - RAM.10 - 10 - RAM.WE# - 11 - RAM.A9 - 12 - RAM.A8 - 13 - RAM.A7 - 14 - GND Ground 15 - GND Ground 16 - RAM.A5 - 17 - RAM.A6 - 18 - RAM.OE# - 19 - RAM.A4 - 20 - RAM.A3 - 21 - 5V0 Vcc 22 - LXRESET# - 23 - RAM.D2 - 24 - RAM.A1 - 25 - 5V0 Vpp 26 - RAM.A0 - 27 - RAM.D0 - 28 - RAM.D7 - 29 - RAM.D5 - 30 - RAM.D6 - 31 - RAM.D1 - 32 - GND Ground 33 - RAM.D2 - 34 - RAM.D4 - 35 - LXA1 - 36 - RAM.D3 - 37 - LXA2 - 38 - 5V0 Vcc 39 - LXA4 - 40 - LXA3 - 41 - LXA6 - 42 - LXA5 - 43 - LXA7 - 44 - LXA9 - 45 - LXA8 - 46 - LXA11 - 47 - LXA10 - 48 - LXA18 - 49 - GND Ground 50 - L68.EXT# - C00000-CFFFFF chip select 51 - LXAS# - Address strobe, asserted earlier than L68.EXT 52 - X14M CLK or I/O From 14.318 MHz oscillator 53 - LXR/W - 54 - GND MODE GND=Special function pins configured as I/O 55 - 5V0 Vcc 56 - BD0 SDI or I/O 57 - BD1 DCLK or I/O 58 - BD2 PRA# or I/O 59 - BD3 PRB# or I/O 60 - BD4 - 61 - BD6 - 62 - BD5 - 63 - BD7 - 64 - BD8 - 65 - BD9 - 66 - GND Ground 67 - BD10 - 68 - BD11 - FPGA connections RAM: RAM.D0-D7, RAM.A0-A10, RAM.OE#, RAM.WE# Note: RAM.CS# is tied to ground. CPU: LXA1-11, LXA18, BD0-15, LXR/W#, LXDS#, LXAS#, LXRESET, L68.EXT# Misc: X14M It is likely that LXAS allows the FPGA to detect cycles early, and the clock allows it to read two bytes sequentially from the address to present to the CPU in case of a 16-bit read from FPGA memory, later qualified by L68.EXT. Likewise the FPGA has 48 bits of internal state so it could capture half or all of a 16-bit write to FPGA RAM and write the individual bytes later. Accesses affect the security state, but one started early with LXAS could be cancelled by a lack of L68.EXT later. PLCC socket pinout (from bottom of board) * D6 D7 D9 D10 D12 D14 XDS R11 R10 D4 D5 D8 GND D11 D13 5V0 D15 A17 RA9 RWE D2 D3 RA7 RA8 D0 D1 GND GND GND 5V0 RA6 RA5 X14M XR/W RA4 ROE XCS XAS 5V0 RA3 A18 GND RD2 XRST A11 A10 5V0 RA1 A9 A8 A5 A3 5V0 RD3 RD4 GND RD6 RD7 RA0 A7 A6 A4 A2 A1 RD2 RD1 RD5 RD0 ---------------------------------------------------------------------------- 0070A PAL dump ---------------------------------------------------------------------------- /* Dedicated input pins */ pin 1 = LXWP; pin 2 = LXR/W; pin 3 = LXA1; pin 4 = LXA9; pin 5 = LXA10; pin 6 = LXA11; pin 7 = LXA12; pin 8 = LXA17; pin 9 = LXA18; pin 11 = L68.EXT; /* Dedicated output pins */ pin 12 = LETA; pin 13 = NUMFASEL; pin 14 = NUMFROTA; pin 15 = COMMLATCH; pin 16 = 68RD1; pin 17 = 68RD0; pin 18 = 68WR; pin 19 = CGINT; /* Output and output enable equations */ !CGINT = !LXWP & !LXR/W & !LXA1 & !LXA9 & LXA10 & !LXA11 & !LXA12 & !LXA17 & LXA18 & !L68.EXT; !68WR = !LXWP & !LXR/W & LXA9 & !LXA10 & !LXA11 & !LXA12 & !LXA17 & LXA18 & !L68.EXT; !68RD0 = LXR/W & LXA9 & !LXA10 & !LXA11 & !LXA12 & !LXA17 & LXA18 & !L68.EXT; !68RD1 = LXR/W & !LXA1 & !LXA9 & !LXA10 & !LXA11 & !LXA12 & !LXA17 & LXA18 & !L68.EXT; !LETA = LXR/W & !LXA9 & !LXA10 & !LXA11 & !LXA12 & LXA17 & LXA18 & !L68.EXT; !COMMLATCH = !LXWP & !LXR/W & LXA9 & LXA10 & !LXA11 & !LXA12 & !LXA17 & LXA18 & !L68.EXT; !NUMFROTA = !LXWP & !LXR/W & !LXA1 & LXA9 & !LXA10 & !LXA11 & !LXA12 & LXA17 & LXA18 & !L68.EXT; !NUMFASEL = !LXWP & !LXR/W & !LXA9 & LXA10 & !LXA11 & !LXA12 & LXA17 & LXA18 & !L68.EXT; ---------------------------------------------------------------------------- 68EC020 debug connector pinout ---------------------------------------------------------------------------- --- --- --- --- --- ds1 --- --- --- gnd gnd a20 5v0 --- --- --- /ds --- --- sz1 rst --- -a1 a22 a18 --- --- --- --- /as --- --- --- --- --- -a0 a21 a17 --- --- --- r/w --- ds0 sz0 --- clk gnd a23 a19 cpu * --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---------------------------------------------------------------------------- End ----------------------------------------------------------------------------