Sega System 16B sound hardware information by Charles MacDonald WWW: http://cgfm2.emuviews.com Unpublished work Copyright 2003 Charles MacDonald This document is in a very preliminary state and is subject to change. Most everything within has been verified on a System 16 board, but please be aware that my testing methods or interpretations of results could be flawed. I can't guarantee that everything is 100% accurate. Last updated 11/22/03 [11/22/03] - Simplified sample ROM banking description [11/21/03] - Initial release Table of contents: 1. Overview 2. Timing 3. Address decoding 4. uPD7759 data output / status input port 5. Sound control latch 6. Sample ROM banking 7. Sound command latch 8. Miscellaneous 9. Disclaimer ---------------------------------------------------------------------------- Overview ---------------------------------------------------------------------------- The sound hardware consists of a Z80-B, YM2151, and uPD7759. The Z80 has access to 2K of work RAM, 32K of program ROM, and up to 1MB of sample ROM in units of 16K banks. ---------------------------------------------------------------------------- Timing ---------------------------------------------------------------------------- An 8.00 MHz oscillator is connected to a divide-by-2 circuit that runs the YM2151 at 4 MHz. The Z80 is also connected to the circuit, but it's clock source comes from elsewhere on the board, which I have not determined yet. The uPD7759 is connected to a 640 KHz ceramic resonator. ---------------------------------------------------------------------------- Address decoding ---------------------------------------------------------------------------- The 315-5214 custom chip (a Signetics CK2605 PLA) is used to handle address decoding. It has 10 inputs from the Z80 and uPD7759, and 8 outputs. The following table shows what input states are needed for the corresponding outputs to be driven low, except for the Z80 D7 output which follows the uPD7759 /BUSY input when reading ports $80-$BF, otherwise it is tristated. A15 A14 A7 A6 /MREQ /IORQ /M1 /RD /WR /BUSY 0 x x x 0 x x x x x Program ROM /CS 1 0 x x 0 x x x x x Sample ROM /CS 1 1 x x 0 x x x x x Work RAM /CS x x 0 0 x 0 1 x x x YM2151 /CS x x 0 1 x 0 1 x x x CLK pin of sound control latch x x 1 0 x 0 1 x 0 x uPD7759 /CS x x 1 0 x 0 1 0 1 0 Z80 D7 = 0 x x 1 0 x 0 1 0 1 1 Z80 D7 = 1 x x 1 1 x 0 1 x x x Sound command latch strobe This gives the following memory and I/O port maps: $0000-$7FFF : Program ROM (32K) $8000-$BFFF : Sample ROM bank (16K) $C000-$FFFF : Work RAM (2K) Most games access the work RAM at $F800-$FFFF only. $00-$3F : YM2151 $40-$7F : uPD7759 data input port (write) uPD7759 /BUSY signal in D7 (read) $80-$BF : Sound control latch (write) $C0-$FF : Sound command latch (read) In most cases, the 315-5214 will enable the corresponding memory or device regardless of reads or writes. It would seem that some cases (writing to ROM) would cause both the Z80 and enabled item to try and drive the data bus at the same time. Or in the case of reading the sound control output latch, it would latch whatever garbage data was left on the data bus. Of course no software does this, but it's interesting to point out. The work RAM, YM2151, and uPD7759 registers are repeatedly mirrored throughout the ranges they are assigned to. ---------------------------------------------------------------------------- uPD7759 data output / status input port ---------------------------------------------------------------------------- All games that I know of use the uPD7759 in slave mode, where the Z80 is responsible for feeding it ADPCM data during sample playback. This port is used for that purpose when written to. Reading bit 7 returns the uPD7759 /BUSY flag state directly from the chip itself. Bits 6-0 are undefined. The /DRQ pin is connected to /NMI so the uPD7759 can interrupt the Z80 when it needs more sample bytes. The NMI handlers in the games I've looked at are written to execute very quickly, usually something like: .org $0066 exx ld b, (hl) out (c), b inc hl exx retn With C = $80 and HL = $8000-$BFFF. Presumably there isn't a lot of time after /DRQ goes low to write more sample data. ---------------------------------------------------------------------------- Sound control latch ---------------------------------------------------------------------------- The value written this latch has the following purpose: D7 : uPD7759 mode control D6 : To /RESET input of uPD7759 D5 : To pin A17 of CN4. (Sample ROM bank select) D4 : To pin B18 of CN4. (Sample ROM bank select) D3 : To pin A18 of CN4. (Sample ROM bank select) D2 : To pin B19 of CN4. (Sample ROM bank select) D1 : To pin A19 of CN4. (Sample ROM bank select) D0 : To pin B20 of CN4. (Sample ROM bank select) Bit 7 of the latch is inverted (by a 74LS00) and fed into several sources: - The /2G input of a 74LS125 which connects Z80 /WR to AEN/WR of the uPD7759 when low. - The /MD pin of the uPD7759. - The /1G,/2G inputs of a 74LS244 which connects the Z80 data bus to the ASD7-0 inputs of the uPD7759 when low. The I7-0 message select inputs are tied to ground, the /ST pin seems to only be connected to +5V by a pull-up resistor, and the address bus isn't connected to anything nor are the significant bits latched by ALE. So, it would appear that putting the chip into standalone mode would not work as expected. Bit 6 can be used to reset the uPD7759. It seems that this would be more useful in standalone mode than in slave mode to make the chip re-read the ROM header. Bits 5-0 go to CN4 and are used for sample ROM banking. This is entirely dependant on the type of ROM board used. ---------------------------------------------------------------------------- Sample ROM banking ---------------------------------------------------------------------------- All sample ROMs have address lines A13-A0 connected to the Z80 address bus. The remaining signals come from the address decoding PAL, sound control latch, and hardware on the ROM board: CN4 pin assignments: B17 - Sample ROM /OE from PAL (For Z80 access to $8000-$BFFF) A17 - Sound control latch bit 5 A18 - Sound control latch bit 4 B18 - Sound control latch bit 3 A19 - Sound control latch bit 2 B19 - Sound control latch bit 1 A20 - Sound control latch bit 0 ============================================================================ 171-5358 (Shinobi, Tough Turf) ============================================================================ Has four sockets (A8-A11) that can use 27256 or 27512 EPROMs depending on the jumper settings. Control latch values D5 : /CS for ROM at A11 D4 : /CS for ROM at A10 D3 : /CS for ROM at A9 D2 : /CS for ROM at A8 D1 : A15 for all ROMs (Or ignored for 27256's) D0 : A14 for all ROMs ============================================================================ 171-5797 (E-Swat, Golden Axe) ============================================================================ Has two sockets (A11, A12) that can use 27C010 or 27C020 EPROMs. Control latch values D5 : Unused D4 : A17 for all ROMs D3 : ROM select 0=A11, 1=A12 D2 : A16 for all ROMs D1 : A15 for all ROMs D0 : A14 for all ROMs ============================================================================ 171-5704 (Tetris) 171-5521 (Heavyweight Champ) ============================================================================ Has two sockets (A11, A12) that can use 27512 or 27C010 EPROMs. The 171-5521 is nearly identical to the 171-5704, except for the jumpers are soldered-in resistors and not jumper blocks. Control latch values D5 : Unused D4 : Unused D3 : ROM select 0=A11, 1=A12 D2 : /OE for all ROMs D1 : A15 for all ROMs D0 : A14 for all ROMs Pin 2 (A16) of both sockets is connected to two jumpers labeled S1 and S2: S2 A-B (Closed on Tetris and Heavyweight Champ) S1 C D (Open) A,C go to pin 2 of the sample ROM sockets. D is ground. B goes to pin A9 of CN3. Tetris has no sample ROMs and Heavyweight Champ has 64K ROMs, so neither actually use pin 2. I haven't been able to find the source of pin A9, so it isn't understood how to control pin 2 via software. ---------------------------------------------------------------------------- Sound command latch ---------------------------------------------------------------------------- The Z80 data bus and /INT pin are connected to the 315-5195 chip. When the 68000 writes a sound command to offset $0007 of the configuration registers (usually $FE0007, but any unmapped region will work; OutRun uses $FFFF07 and Alien Syndrome uses $C00007) it strobes /INT low and latches bits 7-0 of the 68000 data bus. The sound command is usually processed in the Z80 INT interrupt handler, which reads port $C0. This sends a pulse to the 315-5195, making it output the latched sound command to the Z80 data bus. I don't know if reading the sound command latch clears the /INT output to the Z80 (likely), or if this is done automatically. The 8051 MCU is connected to the 315-5195 and can also send sound commands. ---------------------------------------------------------------------------- Miscellaneous ---------------------------------------------------------------------------- Pin assignments for the 315-5214 chip: +----v----+ A15 |01 i 20| +5V A14 |02 i o 19| Sound command latch strobe A7 |03 i o 18| Work RAM /CS A6 |04 i o 17| YM2151 /CS /MREQ |05 i o 16| uPD7759 /CS /IORQ |06 i o 15| CLK pin of sound control latch /M1 |07 i o 14| Program ROM /CS /RD |08 i o 13| Sample ROM /OE /WR |09 i o 12| Z80 D7 GND |10 i 11| uPD7759 /BUSY +---------+ The MB3771 power monitor chip outputs a system-wide /RESET signal which is connected to the YM2151 and Z80. The sound control latch (controlling the reset input of the uPD7759) has it's CLR input tied to D7 of the miscellaneous output latch (at offset $0001 in the I/O region) which in turn has it's CLR input tied to /RESET. The YM2151 /IRQ output doesn't seem to be connected to anything, and therefore isn't usable. The timers status flags can still be polled to regulate music playback. ---------------------------------------------------------------------------- Disclaimer ---------------------------------------------------------------------------- If you use any information from this document, please credit me (Charles MacDonald) and optionally provide a link to my webpage (http://cgfm2.emuviews.com/) so interested parties can access it. The credit text should be present in the accompanying documentation of whatever project which used the information, or even in the program itself (e.g. an about box). Regarding distribution, you cannot put this document on another website, nor link directly to it.